To test an integrated circuit (IC), it is known to subject logic elements of the IC to a stress test. E.g., the chip comprising the IC can be placed in a burn-in oven where environmental conditions can be controlled. E.g., an elevated temperature can be applied.
In reference implementations, an Automated Test Pattern Generation (ATPG) pattern signal which is loaded into the burn-in oven and, fed to IC via scan pins, to the logic elements. The ATPG signal is a pseudorandom test pattern which intends to toggle all or at least a majority of the logic elements between the available states. To facilitate toggling, a test mode can be triggered which effects logical interconnections between the logic elements subject to the test; the logical interconnections enable a series of logic elements to act as a shift register (scan chain) where different clocked states of the ATPG signal iteratively toggle the logic elements of a scan chain. Then, the states of the logic elements of the scan chains may be read out and compared to expected values. Thereby, failure or wear-out of the hardware elements forming the logic elements, e.g., of the transistors, can be detected.
However, such scenarios face certain restrictions and drawbacks. E.g., there may be limited space available in the burn-in oven to store ATPG patterns. On the other hand, it may be required to provide the ATPG signal having a comparably large number of input pins to ensure that almost all or all logic elements are toggled. This requires significant efforts in signal routing which may be complex due to the limited space available.